A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications
نویسندگان
چکیده
Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.
منابع مشابه
Search Based Weighted Multi-Bit Flipping Algorithm for High-Performance Low-Complexity Decoding of LDPC Codes
In this paper, two new hybrid algorithms are proposed for decoding Low Density Parity Check (LDPC) codes. Original version of the proposed algorithms named Search Based Weighted Multi Bit Flipping (SWMBF). The main idea of these algorithms is flipping variable multi bits in each iteration, change in which leads to the syndrome vector with least hamming weight. To achieve this, the proposed algo...
متن کاملSearch Based Weighted Multi-Bit Flipping Algorithm for High-Performance Low-Complexity Decoding of LDPC Codes
In this paper, two new hybrid algorithms are proposed for decoding Low Density Parity Check (LDPC) codes. Original version of the proposed algorithms named Search Based Weighted Multi Bit Flipping (SWMBF). The main idea of these algorithms is flipping variable multi bits in each iteration, change in which leads to the syndrome vector with least hamming weight. To achieve this, the proposed algo...
متن کاملLow Power Error Correcting Codes Using Majority Logic Decoding
A low-density parity-check (LDPC) code is a linear error correcting code, and is used for transmitting message over a noisy transmission channel. A new class of error correcting codes called EG-LDPC (Euclidean Geometry-LDPC) codes and its encoder and decoder architectures for nanomemory applications is designed. EG-LDPC codes also have fault secure detection capability. One step majority logic ...
متن کاملBelief Propagation Based Combined Decoding Scheme for LDPC-coded OFDM with PTS as PAPR Reduction
This paper proposes belief propagation based combined decoding scheme for low-density parity-check (LDPC)-coded orthogonal frequency-division multiplexing (OFDM) system with a peak-to-average power ratio (PAPR) reduction using the partial transmit sequence (PTS), which does not transmit PTS side information about the phase factors. Keywords— Belief Propagation (BP), Partial Transmit Sequence (P...
متن کاملAn Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control
A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره 2015 شماره
صفحات -
تاریخ انتشار 2015